Embedded Solutions CompactPCI F301-3U User Manual Page 17
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PowerPC and Nios-based
■ 32-bit/33-MHz CompactPCI
®
■ Peripheral slot function
■ FPGA 12,000 LEs (approx. 144,000 gates)
■ Nios
®
II soft processor
■ 32 MB SDRAM, 2 MB Flash
■ Flexible FPGA-Flash structure
■ Open platform FPGA development package
■ Support of Wishbone and Avalon
®
bus
■ -40 to +85°C with qualified components
CPU
■ Nios
®
II soft processor, 33MHz
Memory
■ 512 bytes instruction cache and 512 bytes
data cache integrated in Nios
®
II
■ 32MB SDRAM system memory
■ Soldered
■ 133MHz memory bus frequency
■ 2MB boot Flash
I/O
■ One RS232 UART (COM10)
■ D-Sub connector at front panel
■ Data rates up to 115kbits/s
■ 60-byte transmit/receive buffer
■ Handshake lines: full support
■ For debugging
■ Three 10-pin connectors
■ For FPGA-controlled functions
■ For use of SA-Adapters
™
■ One receptacle for direct SA-Adapter
™
connection at the front
■ Two receptacles for direct connection of
long SA-Adapters
™
at the front
■ Two optional plugs for on-board connection
via ribbon cable
■ Different physical layers through
SA-Adapters
™
: RS232, RS422, RS485, TTY,
Ethernet, CAN bus, binary I/O, audio, PS/2
■ One optional 40-pin plug connector
■ For FPGA-controlled functions
■ For use of SA-Adapters
™
■ For on-board connection via ribbon cable
■ Different physical layers through SA-
Adapters
™
: RS232, RS422, RS485, TTY,
Ethernet, CAN bus, binary I/O, audio, PS/2
FPGA
■ Standard factory FPGA configuration:
■ Nios
®
II soft processor
■ 16Z014_PCI - PCI to Wishbone interface
■ 16Z052_GIRQ - Global Interrupt Contr. (Nios
®
)
■ 16Z052_GIRQ - Global Interrupt Contr. (CPU)
■ 16Z069_RST - Reset Controller
■ 16Z043_SDRAM - SDRAM controller (32MB)
■ 16Z045_FLASH - Flash interface
■ 16Z025_UART - UART contr. (contr. COM10)
■ The FPGA offers the possibility to add
customized I/O functionality. See website.
Miscellaneous
■ Four user LEDs, FPGA-controlled
■ Local PCI Bus
■ 32-bit/33-MHz, 3.3V V(I/O)
■ Compliant with PCI Specification 2.2
CompactPCI
®
Bus
■ Compliance with CompactPCI
®
Core
Specification PICMG 2.0 R3.0
■ Peripheral slot
■ 32-bit/33-MHz PCI
■ V(I/O): +3.3V
■ Only one slot required on 3U cPCI
®
backplane
■ More supplementary CompactPCI
®
slots
required depending on SA-Adapters
™
Electrical Specifications
■ Supply voltage/power consumption:
■ +5V (-3%/+5%), current depends only on
mounted SA-Adapters
™
■ +3.3V (-3%/+5%), 500mA typ.
■ MTBF: 308,000h @ 40°C (derived from
MIL-HDBK-217F)
Nios® II
GPIO for
LEDs
IP Core
IP Core
Wishbone to
Avalon®
Bridge
Avalon® to
Wishbone
Bridge
IP Core
PCI Slave
Flash
Interface
SDRAM
Interface
2 MB boot
Flash
32MB SDRAM
IP Core
IP Core
UART
COM10
Compact PCI J1
SA-
Adapter™
SA-
Adapter™
F
F
SA-
Adapter™
SA-
Adapter™
SA-
Adapter
™
FPGA
F
B
Front Panel
On Board
Avalon® Bus
Wishbone Bus
10-pin
receptacle
B
10-pin
receptacle
B
SA-
Adapter
™
SA-
Adapter
™
SA-
Adapter
™
Optional
40-pin plug
(can be assembled on request)
B
B
B
Optional 10-pin plugs (can
be assembled on request)
F206N – 3U CompactPCI
®
Nios
®
II Slave Board
MEN 3U CompactPCI and CompactPCI Express
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